Home Chip Fab

Layout was done in Magic VLSI for a 4 mask PMOS process (active/doped area, gate oxide, contact window, and top metal.) PMOS has advantages over NMOS as far as mobile ionic contamination that lends it to being fabricated in a garage. Positive photoresist (AZ MiR 701 for SiO2 patterning and AZ 4210 for Al layer) is spun on at around 3000rpm yielding a film of about 1.5μm for the AZ MiR 701 or 3.5μm for the AZ 4210 which is soft baked at 90C on a hotplate.Lithography process detailsThe active area mask is exposed with my Mark IV maskless photolithography stepper at 365nm UV and the pattern is developed in TMAH or KOH solution depending on the resist.The resist pattern is then hard baked and a number of other tricks are used to ensure good resist adhesion and chemical stability during the following HF etch step which transfers that pattern to the oxide layer and opens windows to the bare silicon surface for doping. Since the starting wafer for PMOS here is N-type, I am doing P diffusions of Boron for the source/drain regions and am targeting a sheet resistance in diffused regions of 100 to 250 Ω/sq.The above mentioned patterning steps are then repeated twice for the gate oxide layer and then the contact layer. Then, since the whole wafer has been oxidized during the doping step, contact windows must be etched for the metal layer to make connection with source/drain doped regions. Taking 5 traces with -1V Vgs increment requires about a -8V body/substrate bias to overcome fixed charges (positive impurity ions trapped under gate) and lattice defects in the gate region and yield the expected graph.The chip can also be wired as a 3 stage ring oscillator, the classic test for a new IC fabrication process:Showing a natural frequency of around 5kHz for 3 stages, limited mainly by excess the gate to source capacitance due to lithography alignment limitations.Chips can be tested easily and repeatably by probing or wire bonding.Electrical characteristics of Al/Si junctions are characterized as well and show the expected results. These issues combine to leave you with poor pattern definition and often complete photoresist lifting during etch.The steps I have found to mitigate these issues are (in order): dehydration bake, HMDS vapor prime, thick resist coating, hard bake, and buffered oxide etch.First, SiO2 is thermally grown on a test wafer using a water vapor source on a nearby hotplate to fill the furnace with steam during oxidation. It is scalable to any reasonable size and contains 2 differential amplifier circuits (seen on right and middle) and a number of diodes/resistors and other test features on the left.The design requires 4 masks for fabrication: active/diffusion, gate oxide, contact, and metal.Fiducials should be added for subsequent layer alignment. This starts serious outgassing in the chamber and without prior cleaning and bake out quickly raises the pressure to non-workable pressures and the deposition rate slows.I added a second turbo pump to raise the pumping speed/gas throughput (previously 110L/s and now an additional 50L/s) and to tolerate higher outgassing.It was also noted that the evaporation of Al with lots of H2O vapor in the chamber (no baking) leads to a reduction of chamber pressure (presumably the formation of Al2O3 with H2O) and the production of H2 as seen on an RGA.Final process:Tall particles can easily short out the thin gate oxide in these devices, as shown under my SEM. This poses an issue for making such devices in a garage; the gate oxides must be grown thicker to mitigate shorted devices which leads to a higher threshold voltage for the FET.(Click on image to enlarge)Progress in developing the metalization process for the home chip lab.