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Jim Salter
Jun 22
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Ian Cuttress
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Today, RISC-V CPU design company SiFive launched a new processor family with two core designs: P270 (a Linux-capable CPU with full support for RISC-V's vector extension 1.0 release candidate) and P550 (the highest-performing RISC-V CPU to date).For those not immediately familiar with RISC-V, it is a relatively new CPU architecture which takes advantage of Reduced Instruction Set Computer (RISC) principles. Generic RISC-V designs feature reserved opcodes, which designers of specific RISC-V CPUs may then take over to provide additional, arbitrary functionality.The ability to "take over" reserved opcodes allows for greatly streamlined ASIC design, since both specialized instructions and general controller functionality can be provided on a single die—and without CPU architects needing to reinvent any wheels to provide the generic controller functionality.For the moment, RISC-V is not a serious competitor to either Arm or x86 in the general-purpose processor space, but it's heavily used in the microcontroller space, due in part to its extensibility and inexpensive licensing. P270 is SiFive's first CPU to fully support the optional RISC-V vector extension 1.0 release candidate, and P550 is SiFive's highest-performing RISC-V processor to date—also making it, as far as we know, the highest-performing RISC-V processor available.As you'd expect from the "release candidate" rider, RISC-V's "V" optional instruction set is not yet a frozen standard.
As said here by Jim Salter